Intel's Nova Lake Processors May Finally Bring Back AVX-512

It’s been nearly six years since Intel quietly dropped AVX-512 from its consumer processors. Now, evidence is mounting that the company is about to reverse course.

Patches submitted to the Linux kernel confirm that Intel’s next-generation Nova Lake architecture, along with future client-class CPUs, will support the AVX-512 instruction set extension. The news was first reported by Wccftech after spotting the relevant kernel commits.

AVX-512 is an instruction set extension designed for high-throughput parallel computing. It processes wider data vectors in a single operation compared to standard AVX, making it valuable for scientific computing, media encoding, encryption, compression, and certain AI inference workloads. It last appeared in an Intel client processor with Tiger Lake — the 11th-gen Core series launched in September 2020.

The removal started with Alder Lake, Intel’s 12th-gen family, which introduced the hybrid architecture combining Performance-cores (P-cores) and Efficiency-cores (E-cores). Because the smaller E-cores did not support AVX-512, Intel disabled the feature across all cores for consistency.

Intel hinted at a possible return last year through patches for AVX 10.2, a new instruction set specification that appeared to bridge the gap between server and client CPU features. The latest Linux kernel patches go further — they explicitly tag Nova Lake and future client CPU families for AVX-512 enablement.

The performance difference is measurable. Wccftech tested AMD’s Ryzen 9 9950X, which supports AVX-512, and found up to 43% improvement over standard AVX instructions in workloads optimized for the wider vectors.

Nova Lake is expected to succeed Arrow Lake in Intel’s client CPU roadmap, though Intel has not announced an official launch date. If the patches hold, the return of AVX-512 would mark a significant capability shift for Intel’s desktop and laptop processors — one that developers and power users have been waiting for since 2020.