Lenovo's first RISC-V server is a 48-core machine for AI inference — and it's at WAIC right now

Lenovo showed its first RISC-V server at WAIC 2026 in Shanghai this week. The machine, branded as the Lenovo Wentian WR5219 G5, is a 2U rack-mount server powered by the BlueCore LX500 — a 48-core RISC-V processor designed by Chinese chip company Lanxin.

This is the first time Lenovo has publicly displayed a server built on an open-standard instruction set. For a company that ships millions of x86 servers annually, it is a notable step toward commercial RISC-V hardware.

The LX500 is a server-grade heterogeneous CPU with PCIe 5.0 lanes and DDR5 memory — specs that put it roughly on par with entry-level x86 server chips on paper. Lenovo is positioning the WR5219 G5 for AI inference, virtualization, scientific computing, and big data analytics, the workloads that drive most of today’s data center demand.

The server offers flexible storage, memory, and I/O configurations, letting buyers tailor the hardware to their specific use case rather than buying a fixed spec. Lenovo says the machine is compatible with both international chip architectures and China’s domestic CPU and GPU ecosystem — a dual-compatibility approach that makes sense in a market where buyers increasingly hedge between global supply chains and domestic alternatives.

RISC-V has been gaining momentum in China as an alternative to Arm and x86, particularly among companies that want to design their own chips without paying licensing fees. Lenovo’s decision to build a production-style server around the architecture suggests the ecosystem has matured beyond microcontrollers and embedded systems. But software readiness remains the open question. RISC-V server software stacks exist — Linux has had upstream support for years — but enterprise-grade virtualization, container orchestration, and AI frameworks are still catching up.

Lenovo has not announced pricing or general availability for the WR5219 G5. The WAIC demo confirms the hardware works. Whether the software ecosystem can match what x86 and Arm have built over decades is the next milestone.